rggen 0.31.3
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
Gemfile:
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安裝:
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Runtime 相依性套件 (6):
rggen-c-header
~> 0.4.0
rggen-core
~> 0.31.2
rggen-default-register-map
~> 0.31.0
rggen-markdown
~> 0.25.0
rggen-spreadsheet-loader
~> 0.24.0
rggen-systemverilog
~> 0.31.0
Development 相依性套件 (1):
bundler
>= 0
擁有者:
推送者:
作者:
-
Taichi Ishitani
SHA 256 總和檢查碼:
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