rggen 0.31.3

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.

Gemfile:
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instalar:
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Versões:

0.33.3 July 20, 2024 (16 KB)
0.33.2 June 11, 2024 (16 KB)
0.33.1 January 23, 2024 (16 KB)
0.33.0 January 22, 2024 (16 KB)
0.32.2 January 03, 2024 (16 KB)
0.31.3 October 18, 2023 (16 KB)

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Runtime Dependencies (6):

rggen-c-header ~> 0.4.0

rggen-core ~> 0.31.2

rggen-default-register-map ~> 0.31.0

rggen-markdown ~> 0.25.0

rggen-spreadsheet-loader ~> 0.24.0

rggen-systemverilog ~> 0.31.0

Development Dependencies (1):

bundler >= 0

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Donos:

Pushed by:

Autores:

Taichi Ishitani

SHA 256 checksum:

Total de downloads 99.897

Desta versão 643

Versão lançada:
October 18, 2023 2:05am

Licença:
MIT

Versão Requerida do Ruby: >= 2.7

New versions require MFA: true

Version published with MFA: true

Links:

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