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rggen 0.33.3

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to control and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.

Gemfile:
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Versões:

  1. 0.33.3 July 20, 2024 (16 KB)
  2. 0.33.2 June 11, 2024 (16 KB)
  3. 0.33.1 January 23, 2024 (16 KB)
  4. 0.33.0 January 22, 2024 (16 KB)
  5. 0.32.2 January 03, 2024 (16 KB)
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Runtime Dependencies (6):

rggen-c-header ~> 0.5.0
rggen-core ~> 0.33.1
rggen-default-register-map ~> 0.33.1
rggen-markdown ~> 0.26.0
rggen-spreadsheet-loader ~> 0.25.3
rggen-systemverilog ~> 0.33.0
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Donos:

Pushed by:

Autores:

  • Taichi Ishitani

SHA 256 checksum:

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Total de downloads 99.896

Desta versão 1.172

Versão lançada:

Licença:

MIT

Versão Requerida do Ruby: >= 3.0

New versions require MFA: true

Version published with MFA: true

Links:

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